In the fabrication of integrated circuit devices, openings such as contact holes and via holes are utilized to interconnect different layers of the integrated circuit device. For instance, a contact hole typically connects a semiconductor substrate to a conductive layer, and a via hole typically connects one conductive layer to another. According to conventional methods, contact holes and via holes (collectively referred to hereafter as contact holes) can be formed by exposing a portion of the semiconductor substrate or a surface of the conductive layer by etching an inter-insulating layer formed on the semiconductor substrate or the conductive layer.
As the integration density of integrated circuit devices increases to achieve higher speeds, higher level functionality, and smaller sizes, the area available for each cell of the integrated circuit device generally diminishes. Consequently, the area occupied by each contact hole of the cell may also be reduced. The site of a contact hole is of interest because the contact hole may affect process margins for subsequent processes. For instance, a small contact hole can increase the process margin for a subsequent step of forming a conductive layer that fills the contact hole. Accordingly, much attention is being paid to contact holes in an effort to advance the development of smaller contact holes and the corresponding methods for the fabrication of the same.
Various methods for forming contact holes have been proposed in the prior art. In particular, an example of one such method for forming a contact hole is described below with reference to FIGS. 1 to 3.
FIGS. 1 to 3 are sectional views showing steps of a method for forming a contact hole according to the prior art. With reference to FIG. 1, a field oxide film 12 for device isolation is formed on a semiconductor substrate 10. A wordline 14 and a first insulating layer 16 that insulates the wordline 14 are sequentially formed on the field oxide film 12. Next, an inter-insulating layer 18 is formed over the first insulating layer 16, providing a planar surface. An etching stop layer 20 is then formed by depositing polysilicon on the inter-insulating layer 18, and a second insulating layer 22 is formed by depositing an insulating material on the etching stop layer 20. Photoresist is then coated and patterned on the second insulating layer 22, thereby forming the photoresist pattern 24 to expose a portion of the second insulating layer 22 for forming a contact hole, as shown in FIG. 1.
With reference to FIG. 2, the second insulating layer 22 is patterned using the photoresist pattern 24 as an etching mask. The photoresist pattern 24 is removed and an oxide layer is deposited on the second insulating layer 22 and the etching stop layer 20. The oxide layer is then anisotropically etched to form an oxide spacer 26 on the sidewalls of the patterned second insulating layer 22. Next, the stop layer 20 is selectively etched using the oxide spacer 26 as an etching mask.
A contact hole (a) is then formed as shown in FIG. 3. In particular, the inter-insulating layer 18 and the first insulating layer 16 are etched using the spacer 26 as an etching mask to form the contact hole (a) exposing a portion of the semiconductor substrate 10. The second insulating layer 22 and the spacer 26 are then removed.
According to the method described above, the portion of the semiconductor substrate exposed by the patterned second insulating layer 22 is reduced by the size of the spacer 26. Therefore, the contact hole (a) formed by the above method may be smaller than that provided by a conventional photolithography process. The etching stop layer 20, which is preferably formed of polysilicon, may also prevent damage to the inter-insulating layer 18 during formation of the oxide spacer 26.
While the width of contact holes formed by the method discussed above can be reduced, reductions in width may result in corresponding increases in the aspect ratio of the contact hole. For purposes of this disclosure, the aspect ratio of a contact hole denotes a ratio of the height of the contact hole with respect to the width of the contact hole. In practice, the inter-insulating layer 18 illustrated in FIG. 3 may maintain a predetermined thickness while the width of the contact hole decreases when increasing the density of the integrated circuit device. As a result, the aspect ratio of the contact hole may be unfavorably increased.
When a conductive or metal layer is formed in a contact hole having an increased aspect ratio, the step coverage of the metal wiring in the contact hole may be poor. Thus, the prior method described herein may lead to a wire opening or a void within the contact hole.